Usual conventional hardware is not changeable during the run time. However, different functionalities of conventional hardware may be achieved by executing different software. Contrary to this, hardware made of hardware-configurable logic circuits is not unalterable, but may be changed at any time. Hardware-configurable logic circuits may be reprogrammed or reconfigured at the hardware level with the aid of a hardware description language (HDL). Different functionalities may thus be assigned to the hardware-configurable logic circuits. Hardware-configurable logic circuits may be so-called field-programmable gate arrays (FPGAs), for example.
To reconfigure FPGAs, individual circuit areas of an FPGA may be interconnected differently. A configuration of hardware elements in the individual circuit areas is changed for this purpose. With the aid of these different configurations, a different function or functionality of the circuit areas, and thus of the FPGA, is achieved. Such hardware elements may be, for example, lookup tables (LUT), multiplexers (Mux), interconnections between logic instances (e.g., programmable interconnect points) and/or global resources (Clock, Vcc, GND).
Information about different hardware configurations (configuration data) may be stored in a so-called configuration memory. The hardware elements within individual circuit areas and the circuit areas among each other are interconnected with each other according to these configuration data in the configuration memory. In particular certain subareas of the configuration memory may contain configuration data for different circuit areas of the FPGA.
To satisfy safety-critical requirements, faults of a hardware-configurable logic circuit must be detected and treated preferably quickly. Such a fault occurs, for example, when individual circuit areas of the hardware-configurable logic circuit are incorrectly interconnected with each other. Accordingly, an output signal which is provided by the hardware-configurable logic circuit is faulty. For the automotive field, safety-critical requirements are defined in an ISO standard. According to this standard, a fault must be detected and treated within a so-called fault tolerant time. The fault tolerant time describes the time between the occurrence of a fault and a hazardous event. A time duration between the occurrence and detection of the fault is described as the fault detection time.
To check a hardware-configurable logic circuit for faults, it is possible, for example, to cyclically check all subareas of the configuration memory. It is thus checked whether the correct configuration data for all circuit areas of the hardware-configurable logic circuit are stored in all subareas. However, this may take up a comparatively long time duration of 10 ms or more. This, in turn, may result in a high fault detection time. To be able to adhere to the fault tolerant time with certainty, however, it is desirable to keep the fault detection time as short as possible.
It is therefore desirable to provide an option of carrying out a fault check of a hardware-configurable logic circuit quickly and reliably.